Semiconductor wafer, method of producing semiconductor wafer, and heterojunction bipolar transistor

ABSTRACT

Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such as InGaAs, by implanting only a small amount of silicon atoms. Such a semiconductor wafer may include a first semiconductor crystal layer, a second semiconductor crystal layer exhibiting a conductivity type that is different from the first layer, a third semiconductor crystal layer exhibiting the conductivity type of the first layer and having a larger band gap than the second semiconductor crystal layer, and a fourth semiconductor crystal layer exhibiting the conductivity type of the first layer and having a smaller band gap than the third semiconductor crystal layer. The fourth semiconductor crystal layer contains a first element that generates a first carrier of a corresponding conductivity type and a second element that generates a second carrier of a corresponding conductivity type.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor wafer, a method ofproducing a semiconductor wafer and a heterojunction bipolar transistor.

2. Related Art

Group III-V compound semiconductor devices such as heterojunctionbipolar transistors may have a connection region made of a semiconductorbetween the semiconductor region providing the operable region and themetal electrode to electrically connect them together. Such asemiconductor connection region preferably forms an ohmic contact withthe metal electrode and has low contact resistance. In addition, theconnection region itself preferably has low electrical resistance. Forthis reason, the semiconductor used to form the connection region isoften a narrow band-gap semiconductor doped with a large amount ofimpurity atoms.

For example, when a heterojunction bipolar transistor has a collectormade of n-type GaAs, a base made of p-type GaAs, an emitter made ofn-type InGaP, and a sub-emitter made of n-type GaAs, a contact layermade of n-type InGaAs is formed between the emitter electrode made ofmetals and the sub-emitter as the above-described semiconductorconnection region. Japanese Patent Application Publication No. 7-22327discloses in Paragraphs [0002] to [0006] the problems caused by the useof the n-type InGaAs layer as the connection region and exemplarysolutions for the problems.

Specifically speaking, Japanese Patent Application Publication No.7-22327 discloses as follows.

“In the conventional art, . . . N⁺-type In_(y)Ga_(1-y)As crystal layer 3is further vapor-deposited on element body 2, which provides theoperable region (the collector, base, emitter and the like), and thecrystal layer 3 is used as a non-alloy resistance contact region . . . .The N⁺-type In_(y)Ga_(1-y)As crystal layers 3 and 4 are typically formedby metal organic chemical vapor deposition (MOCVD). In this case, thedopant materials to be used typically include disilane (Si₂H₆) ormonosilane (SiH₄).”

“When the N⁺-type In_(y)Ga_(1-y)As crystal layer is used as a non-alloyresistance contact region . . . , the indium ratio y is typically atleast set to 0.5 or higher. Here, in order to vapor-deposit InGaAscrystal layers having such an indium ratio, . . . the suitabletemperature is 400° C. to 500° C., which is relatively low. On the otherhand, the dopant materials of disilane and monosilane are highlyefficiently implanted within a temperature range of 600° C. to 800° C.,which is suitable for the vapor-deposition of GaAs crystal layers andAlGaAs layers, but significantly poorly implanted within the temperaturerange that is suitable for the vapor-deposition of InGaAs crystallayers.”

“Therefore, in order to perform heavy doping targeting a concentrationof approximately 5×10¹⁹ cm⁻³, which is required to form non-alloyresistance contact layer . . . , with the use of disilane or monosilaneas the dopant materials within the temperature range of 400° C. to 500°C., which is suitable for the vapor-deposition of InGaAs crystal, thesource gas need to be pumped into the growth chamber at theconcentration that is 10 to 100 times as high as the concentrationemployed for the vapor-deposition of GaAs crystal and AlGaAs crystal.When the source gas is fed at such a high concentration, however, thedopant materials themselves and silicon resulting from thermaldecomposition of the dopant materials contaminate the growth chamber.Thus, it is difficult to grow highly pure crystal.

“The present invention aims to manufacture compound semiconductordevices having improved performances and to prevent the contamination ofthe growth chamber used to manufacture the compound semiconductordevices, by utilizing dopant materials that can be highly efficientlyimplanted at temperatures suitable for vapor-deposition of InGaAs andInAs crystal layers.”

“The above-described problems can be solved by using selenium as thedopant (donor impurity).”

“Selenium is a Group-VI element and serves as a donor impurity. Inaddition, selenium is always stable at relatively low temperaturessuitable for vapor-deposition of InGaAs crystal layers or InAs crystallayers and the activation rate of selenium never degrades.”

Japanese Patent Application Publication No. 7-321058 also discloses inclaim 4 that selenium may be used as the n-type dopant in place ofsilicon.

As disclosed in Japanese Patent Application Publications Nos. 7-22327and 7-321058, the use of Group-VI atoms such as selenium as the n-typedopant can allow the n-type impurity atoms to be implanted at highconcentration into InGaAs, which inevitably requires to be grown at lowtemperatures.

When Group-VI atoms such as selenium are used as the n-type dopant forInGaAs, however, the Group-VI atoms such as selenium remain within theepitaxial growth chamber and may unfavorably contaminate a nextsemiconductor wafer while it is being manufactured. In addition, theGroup-VI atoms such as selenium have higher diffusion coefficient insolids than silicon. The atoms such as selenium may diffuse into theunderlying layers during the epitaxial growth and compromise thereliability of the devices to be manufactured with the layers.

For the above-described reasons, it is preferable to use silicon atomsin place of Group-VI atoms such as selenium, as the n-type dopant forInGaAs crystal. When silicon atoms are used as the dopant, however,sufficient electrical conductivity cannot be achieved unless a largeamount of silicon atoms are implanted as disclosed in Japanese PatentApplication Publication No. 7-22327. The implantation of a large amountof silicon atoms degrades the crystallinity of InGaAs crystal and thusis not preferable.

The objective of the present invention is to provide a technique thatcan impart sufficient electrical conductivity to semiconductor crystalexhibiting low doping efficiency for silicon atoms, such as InGaAs, byimplanting only a small amount of silicon atoms. Another objective ofthe present invention is to provide a technique that can enhance thepurity and crystallinity of semiconductor crystal by implanting asmaller amount of silicon atoms into the semiconductor crystal and thusprovide n-type compound semiconductor crystal with low resistance andexcellent crystallinity.

SUMMARY

To solve the above-described problems, a first aspect of the presentinvention is to provide a semiconductor wafer including: a firstsemiconductor crystal layer exhibiting a first conductivity type that isone of a p-type and an n-type; a second semiconductor crystal layerexhibiting a second conductivity type that is different from the firstconductivity type; a third semiconductor crystal layer exhibiting thefirst conductivity type and having a larger band gap than the secondsemiconductor crystal layer; and a fourth semiconductor crystal layerexhibiting the first conductivity type and having a smaller band gapthan the third semiconductor crystal layer. Here, the firstsemiconductor crystal layer, the second semiconductor crystal layer, thethird semiconductor crystal layer and the fourth semiconductor crystallayer are arranged in an order of the first semiconductor crystal layer,the second semiconductor crystal layer, the third semiconductor crystallayer and the fourth semiconductor crystal layer, the fourthsemiconductor crystal layer contains a first element that generates afirst carrier corresponding to the first conductivity type and a secondelement that generates a second carrier corresponding to the secondconductivity type, and the fourth semiconductor crystal layer has acarrier concentration of 1×10¹⁹ [cm⁻³] or higher and a mobility of 1000[cm²/Vs] or higher according to a Hall effect measurement.

The fourth semiconductor crystal layer may have a carrier concentrationof 2×10¹⁹ [cm⁻³] or higher and a mobility of 1000 [cm²/Vs] or higheraccording to a Hall effect measurement. The fourth semiconductor crystallayer may be an In_(x)Ga_(1-x)As layer (0<×<1) exhibiting n-typeconductivity, preferably an In_(x)Ga_(1-x)As layer (0.4<×<0.8). In thiscase, the first element may be silicon, the second element may becarbon, and the ratio in concentration of carbon to silicon in theInGaAs layer may be 0.15 or lower, preferably 0.15 to 0.01, morepreferably 0.1 to 0.01, most preferably 0.07 to 0.01. The fourthsemiconductor crystal layer may be formed by means of MOCVD using afirst source gas containing a Group-III element and the second element,a second source gas containing a Group-V element and a third source gascontaining the first element. In this case, the fourth semiconductorcrystal layer may be formed with a feed rate ratio of the third sourcegas to the first source gas set to 0.6 or lower, preferably 0.55 to0.01.

A second aspect of the present invention is to provide a method ofproducing a semiconductor wafer, including sequentially epitaxiallygrowing, on a wafer, a first semiconductor crystal layer exhibiting afirst conductivity type that is one of a p-type and an n-type, a secondsemiconductor crystal layer exhibiting a second conductivity type thatis different from the first conductivity type, a third semiconductorcrystal layer exhibiting the first conductivity type and having a largerband gap than the second semiconductor crystal layer, and a fourthsemiconductor crystal layer exhibiting the first conductivity type andhaving a smaller band gap than the third semiconductor crystal layer.Here, the fourth semiconductor crystal layer is formed by means of MOCVDusing a first source gas containing a Group-III element and a secondelement, a second source gas containing a Group-V element and a thirdsource gas containing a first element, the first element generates afirst carrier corresponding to the first conductivity type and thesecond element generates a second carrier corresponding to the secondconductivity type, and the fourth semiconductor crystal layer is formedwith a feed rate ratio of the third source gas to the first source gasset to 0.6 or lower, preferably 0.55 to 0.01.

The fourth semiconductor crystal layer may be formed with a growthtemperature set to 550° C. or lower. The first source gas may contain anIn source gas containing In and a Ga source gas containing Ga. In thiscase, during the formation of the fourth semiconductor crystal layer,the feed rate ratio of the In source gas to the Ga source gas may becontrolled so that the ratio x of In to Ga in the fourth semiconductorcrystal layer is 0.4<×<0.8.

A third aspect of the present invention is to provide a heterojunctionbipolar transistor including the above-described semiconductor wafer.The first semiconductor crystal layer is used as a collector layer, thesecond semiconductor crystal layer is used as a base layer, the thirdsemiconductor crystal layer is used as an emitter layer, and the fourthsemiconductor crystal layer is used as an emitter contact layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view schematically showing a semiconductorwafer 100.

FIG. 2 is a cross-sectional view schematically showing a heterojunctionbipolar transistor 200 manufactured using the semiconductor wafer 100.

FIG. 3 shows a graph indicating how the electron concentration changesas the IV/III ratio changes.

FIG. 4 shows a graph indicating how the mobility changes as the IV/IIIratio changes.

FIG. 5 shows the relation between the electron concentration and themobility for various IV/III ratio values.

FIG. 6 shows a graph indicating how the electron concentration changesas the In ratio changes.

FIG. 7 shows a graph indicating how the mobility changes as the In ratiochanges.

FIG. 8 shows a graph indicating how the resistivity changes as the Inratio changes.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1 is a cross-sectional view schematically showing a semiconductorwafer 100 relating to an embodiment of the present invention. Thesemiconductor wafer 100 is suitably used to manufacture a heterojunctionbipolar transistor (HBT) and includes a support wafer 102 and a stackstructure 104 that is made up by a plurality of compound semiconductorcrystal layers formed on the support wafer 102.

The support wafer 102 is designed to support the stack structure 104 andis not particularly limited in terms of its shape, materials or thelike, as long as the support wafer 102 has necessary levels ofmechanical strength, chemical stability, and thermal stability to formthe respective layers making up the stack structure 104. When the stackstructure 104 is made up by GaAs-based compound semiconductor crystallayers, the support wafer 102 is preferably a semi-insulative GaAswafer. In addition to a GaAs wafer, a silicon wafer, a germanium waferor the like can be used as the support wafer 102.

The stack structure 104 includes a first connection layer 106, a firstsemiconductor crystal layer 108, a second semiconductor crystal layer110, a third semiconductor crystal layer 112, a second connection layer114 and a fourth semiconductor crystal layer 116. The first connectionlayer 106 is a semiconductor crystal layer heavily doped with impurityatoms and has the same conductivity type as the first semiconductorcrystal layer 108. The first connection layer 106 is designed toestablish electrical connection between the first semiconductor crystallayer 108 and electrodes to be later formed. The second connection layer114 is a semiconductor crystal layer heavily doped with impurity atomsand has the same conductivity type as the third semiconductor crystallayer 112 and the fourth semiconductor crystal layer 116. The secondconnection layer 114 is designed to establish electrical connectionbetween the third semiconductor crystal layer 112 and the fourthsemiconductor crystal layer 116.

The first semiconductor crystal layer 108 exhibits a first conductivitytype, which is one of the p-type and the n-type. The secondsemiconductor crystal layer 110 exhibits a second conductivity type thatis different from the first conductivity type. The third semiconductorcrystal layer 112 exhibits the first conductivity type and has a greaterband gap than the second semiconductor crystal layer 110. The fourthsemiconductor crystal layer 116 exhibits the first conductivity type andhas a smaller band gap than the third semiconductor crystal layer 112.The first semiconductor crystal layer 108, the second semiconductorcrystal layer 110, the third semiconductor crystal layer 112 and thefourth semiconductor crystal layer 116 are arranged in the order of thefirst semiconductor crystal layer 108, the second semiconductor crystallayer 110, the third semiconductor crystal layer 112 and the fourthsemiconductor crystal layer 116 as shown in FIG. 1. The fourthsemiconductor crystal layer 116 contains a first atom that generates afirst carrier corresponding to the first conductivity type and a secondatom that generates a second carrier corresponding to the secondconductivity type, and the fourth semiconductor crystal layer 116 has acarrier concentration of 1×10¹⁹ [cm⁻³] or higher and mobility of 1000[cm²/Vs] or higher according to the Hall effect measurements.Preferably, the fourth semiconductor crystal layer has a carrierconcentration of 2×10¹⁹ [cm⁻³] or higher and mobility of 1000 [cm²/Vs]or higher according to the Hall effect measurements.

FIG. 2 is a cross-sectional view schematically showing a heterojunctionbipolar transistor 200 manufactured using the semiconductor wafer 100.As shown in FIG. 2, a first mesa structure made up by the firstsemiconductor crystal layer 108 and the second semiconductor crystallayer 110 is formed on the first connection layer 106, and a second mesastructure made up by the third semiconductor crystal layer 112, thesecond connection layer 114 and the fourth semiconductor crystal layer116 is formed on the first mesa structure. After this, a collectorelectrode 202 is formed so as to be in contact with the first connectionlayer 106, and a base electrode 204 is formed so as to be in contactwith the second semiconductor crystal layer 110. Furthermore, an emitterelectrode 206 is formed so as to be in contact with the fourthsemiconductor crystal layer 116.

In the case of the heterojunction bipolar transistor (HBT) 200 shown inFIG. 2, the first connection layer 106 serves as the sub-collector, thefirst semiconductor crystal layer 108 as the collector, the secondsemiconductor crystal layer 110 as the base, the third semiconductorcrystal layer 112 as the emitter, the second connection layer 114 as thesub-emitter, and the fourth semiconductor crystal layer 116 as theemitter contact. When the first conductivity type is the n-type, the HBT200 is of the npn-type. When the first conductivity type is the p-type,the HBT 200 is of the pnp type.

The HBT 200 is configured such that the band gap of the thirdsemiconductor crystal layer 112 serving as the emitter is greater thanthe band gap of the second semiconductor crystal layer 110 serving asthe base. In this manner, the diffusing current from the emitter to thebase can be guided to flow into the collector without being lost in thebase region, and the diffusing current from the base to the emitter canbe blocked by the heterojunction of the valence band. Accordingly, theHBT 200 can achieve high-speed operation. In addition, the band gap ofthe fourth semiconductor crystal layer 116 serving as the emittercontact is smaller than the band gap of the third semiconductor crystallayer 112. In this way, lowered contact resistance is observed betweenthe emitter electrode 206 and the fourth semiconductor crystal layer116, and increased current density can be achieved for the currentflowing from the emitter electrode 206.

As for the semiconductor wafer 100 of the present embodiment, the fourthsemiconductor crystal layer 116 contains a first atom that generates afirst-conductivity-type carrier and a second atom that generates asecond-conductivity-type carrier, and the fourth semiconductor crystallayer 116 has a carrier concentration of 1×10¹⁹ [cm⁻³] or higher andmobility of 1000 [cm²/Vs] or higher, preferably a carrier concentrationof 2×10¹⁹ [cm⁻³] or higher and mobility of 1000 [cm²/Vs] or higher,which are measured by means of the Hall effect measurements.Accordingly, the fourth semiconductor crystal layer 116 and the emitterelectrode 206 form an ohmic contact, and the semiconductor wafer 100 canachieve lowered contact resistance and lowered resistance of the fourthsemiconductor crystal layer 116.

The carrier concentration of 1×10¹⁹ [cm⁻³] or higher and the mobility of1000 [cm²/Vs] or higher of the fourth semiconductor crystal layer 116can be achieved based on the following findings obtained by theinventors of the present invention from experiments and reviews.

In order that the fourth semiconductor crystal layer 116 may exhibit thefirst conductivity type, the fourth semiconductor crystal layer 116needs to contain such an amount of first atoms that the carriersgenerated by the first atoms are more than offset by the carriersgenerated by the second atoms. In addition, the fourth semiconductorcrystal layer 116 needs to be doped with a large amount of first atomsin order to achieve a carrier concentration (approximately 1×10¹⁹[cm⁻³]) that is enough to lower the contact resistance between thefourth semiconductor crystal layer 116 and the emitter electrode 206 toa required level. Such requirements poses problems in relation to theheavy doping of silicon atoms when the fourth semiconductor crystallayer 116 is, for example, an InGaAs layer, as set forth in the sectionof the related art.

The inventors of the present invention have focused on the fact that thesecond atoms may offset the carriers and found that the amount of firstatoms to be implanted can be reduced by reducing the amount of thesecond atoms to be implanted. In order to reduce the amount of thesecond atoms to be implanted, the fourth semiconductor crystal layer 116may be grown at a higher rate. The fourth semiconductor crystal layer116 can achieve enhanced purity and crystallinity by accomplishing lowerconcentrations of the first and second atoms. In this manner, the fourthsemiconductor crystal layer 116 can achieve mobility of 1000 [cm²/Vs] orhigher while it is ensured that the fourth semiconductor crystal layer116 achieves the necessary carrier concentration.

When the HBT 200 is of the npn-type, the fourth semiconductor crystallayer 116 can be, for example, an n-type In_(x)Ga_(1-x)As layer (0<×<1).In this case, the first atoms are silicon atoms and the second atoms arecarbon atoms, for example. The ratio in concentration of the carbonatoms to the silicon atoms in the InGaAs layer can be 0.15 or lower,preferably 0.15 to 0.01, more preferably 0.1 to 0.01, most preferably0.07 to 0.01. As described above, the carbon atoms, which are the secondatoms, have a low concentration, and the ratio of the carbon atoms tothe silicon atoms, which are the first atoms, is 0.15 or lower. When thefourth semiconductor crystal layer 116 is an n-type In_(x)Ga_(1-x)Aslayer (0<×<1), a carrier concentration of 1×10¹⁹ [cm⁻³] or higher and amobility of 1000 [cm²/Vs] or higher, preferably a carrier concentrationof 2×10¹⁹ [cm⁻³] or higher and a mobility of 1000 [cm²/Vs] or higher,can be achieved if the ratio in concentration of the carbon atoms, whichare the second atoms, to the silicon atoms, which are the first atoms is0.15 or lower.

When the fourth semiconductor crystal layer 116 is an n-typeIn_(x)Ga_(1-x)As layer (0.4<×<0.8), a carrier concentration of 1×10¹⁹[cm⁻³] or higher and a mobility of 1000 [cm²/Vs] or higher, preferably acarrier concentration of 2×10¹⁹ [cm⁻³] or higher and a mobility of 1000[cm²/Vs] or higher, can be also achieved. When the In ratio x is0.4<×<0.8 or relatively high, the InGaAs layer suffers from poorcrystallinity and experiences considerable surface roughness unlessformed at a low temperature of 550° C. or lower. In the presentembodiment, however, the fourth semiconductor crystal layer 116 canachieve a low carbon atom concentration even if grown at a lowtemperature of 550° C. or lower. Thus, the fourth semiconductor crystallayer 116 can achieve a mobility of 1000 [cm²/Vs] or higher while it isensured that the fourth semiconductor crystal layer 116 has a necessarycarrier concentration. Accordingly, even when the In ratio x is0.4<×<0.8, the fourth semiconductor crystal layer 116 of the presentembodiment can achieve a carrier concentration of 1×10¹⁹ [cm⁻³] orhigher and a mobility of 1000 [cm²/Vs] or higher, preferably a carrierconcentration of 2×10¹⁹ [cm⁻³] or higher and mobility of 1000 [cm²/Vs]or higher without causing surface roughness.

For example, the first connection layer 106 is an n⁺-type GaAs layer,the first semiconductor crystal layer 108 is an n-type GaAs layer, thesecond semiconductor crystal layer 110 is a p-type GaAs layer, the thirdsemiconductor crystal layer 112 is an n-type InGaP layer, the secondconnection layer 114 is an n-type GaAs layer, and the fourthsemiconductor crystal layer 116 is an n-type InGaAs layer.

The first connection layer 106, the first semiconductor crystal layer108, the second semiconductor crystal layer 110, the third semiconductorcrystal layer 112 and the second connection layer 114 can be formedusing MOCVD (Metal Organic Chemical Vapor Deposition). The MOCVDtechnique can use as the source gas, for example, TMGa(trimethylgallium), TEGa (triethylgallium), TMIn (trimethylindium), AsH₃(arsine), PH₃ (phosphine) or the like. The carrier gas can be hydrogen.A compound can be alternatively used that is obtained by replacing someof the hydrogen atom groups of the source gas with chlorine atoms orhydrocarbon groups. The reaction temperature can be selected asappropriate within the range of 300° C. to 900° C., preferably 400° C.to 800° C. The thickness can be controlled by appropriately selectingthe amount of the source gas to be fed and the reaction duration.

Likewise, the fourth semiconductor crystal layer 116 cab be formed usingMOCVD using a first source gas containing Group-III atoms and the secondatoms, a second source gas containing Group-V atoms and a third sourcegas containing the first atoms. The formation of the fourthsemiconductor crystal layer 116 is performed with the feed rate ratio ofthe third source gas to the first source gas set to 0.6 or lower,preferably 0.55 to 0.01. It should be noted that the first atomsgenerate the first carriers corresponding to the first conductivity typeand that the second atoms generate the second carriers corresponding tothe second conductivity type.

The first source gas can be TMGa, TEGa and TMIn. The second source gascan be AsH₃. When the first conductivity type is the n-type, the thirdsource gas can be SiH₄ (silane) or Si₂H₆ (disilane). The first sourcegas contains carbon atoms that are to generate holes, which are thesecond carriers.

The carrier gas can be hydrogen. A compound can be alternatively usedthat is obtained by replacing some of the hydrogen atom groups of thesource gas with chlorine atoms or hydrocarbon groups. The reactiontemperature can be set 550° C. or lower. The In ratio can be controlledby regulating the ratio in fed amount between TMIn and one of TMGa andTEGa, which are the first source gas. The ratio in fed amount of the Insource gas to the Ga source gas can be controlled such that the ratio xof the In atoms to the Ga atoms in the fourth semiconductor crystallayer 116 is 0.4<×<0.8. The thickness can be controlled by appropriatelyselecting the amount of the source gas to be fed and the reactionduration.

(Working Example)

A semiconductor wafer of a working example was manufactured bysequentially stacking, on a semi-insulative GaAs wafer (the supportwafer 102), an n⁺-type GaAs layer to serve as the sub-collector (thefirst connection layer 106), an n-type GaAs layer to serve as thecollector (the first semiconductor crystal layer 108), a p-type GaAslayer to serve as the base (the second semiconductor crystal layer 110),an n-type InGaP layer to serve as the emitter (the third semiconductorcrystal layer 112), an n-type GaAs layer to serve as the sub-emitter(the second connection layer 114) and an n-type InGaAs layer to serve asthe emitter contact (the fourth semiconductor crystal layer 116). Then-type InGaP layer to serve as the emitter (the third semiconductorcrystal layer 112) had a larger band gap than the p-type GaAs layer toserve as the base (the second semiconductor crystal layer 110). Then-type InGaAs layer to serve as the emitter contact (the fourthsemiconductor crystal layer 116) had a smaller band gap than the n-typeInGaP layer to serve as the emitter (the third semiconductor crystallayer 112).

The n-type InGaAs layer to serve as the emitter contact (the fourthsemiconductor crystal layer 116) was formed using TEGa and TMIn as theGroup-III source material, AsH₃ as the Group-V source material, andSi₂H₆ as the Group-IV source material. The growth temperature wasappropriately selected within the range of 466° C. to 503° C. and a highgrowth rate was achieved by feeding a large amount of TMIn. Thethickness was 250 nm.

As for the formation of the n-type InGaAs layer (the fourthsemiconductor crystal layer 116), the feed rate ratio of the Group-IVsource material to the Group-III source material (the IV/III ratio) waschanged within the range of 0.07 to 0.51 to manufacture semiconductorwafers of first to fourth working examples. In addition, the In ratiowas changed within the range of 0.5 to 0.68 to manufacture semiconductorwafers of fifth to eighth working examples. For the comparison purposes,the growth rate was lowered to 15.8 nm/min to 19.0 nm/min, and theIV/III ratio was changed within the range of 0.73 to 0.94 to manufacturesemiconductor wafers of first to third comparative examples.

It should be noted that the IV/III ratio is defined based on the actualflow rates of the Group-IV source material and the Group-III sourcematerial as fed from the tanks or bubblers. The actual flow rate of thesource material is calculated as (the gas concentration in thetank)×(the gas flow rate) when the source material is fed from the tankin the gaseous phase, or as (the carrier gas flow rate)×(the vaporpressure of the source material within the bubbler)/(the internalpressure within the bubbler) when the source material is fed through thebubbler. The gas flow rate and the carrier gas flow rate are controlledby a mass flow controller.

Tables 1 and 2 shows the measured values of the growth rate, electronconcentration and mobility for the first to third comparative examples,the first to fourth working examples, and the fifth to eighth workingexamples. Table 2 additionally shows the measured values of theresistivity for the fifth to eighth working examples. Tables 1 and 2also show the measured values of the ratio of the C atom concentrationto the Si atom concentration (the C/Si ratio in concentration) for someof the working examples. Table 1 also shows the measured values for thefirst to third comparative examples. The electron concentration,mobility and resistivity were examined by means of the Hall effectmeasurement technique (the van der pauw method) using the ResiTest 8300Hall Measurement system available from TOYO Corporation under the ASTMF76 standards. The C/Si ratio in concentration was examined by means ofsecondary ion mass spectrometry (SIMS). The In ratio was examined usingthe X-ray diffraction technique. In Tables 1 and 2, CE stands for acomparative example and WE stands for a working example.

TABLE 1 C/Si ELECTRON CONCEN- GROWTH IV/III CONCEN- TRATION RATE RATIOTRATION MOBILITY RATIO (nm/min) (—) (1/cm³) (cm²/Vs) (—) CE1 19.0 0.732.4E+19 970 — CE2 15.8 0.79 2.5E+19 990 0.18 CE3 18.7 0.94 2.5E+19 980 —WE1 27.1 0.07 1.2E+19 1,190 — WE2 27.6 0.26 2.5E+19 1,090 0.05 WE3 25.90.41 2.5E+19 1,060 — WE4 28.3 0.51 1.9E+19 1,020 —

TABLE 2 GROWTH ELECTRON C/Si RATE In RATIO CONCENTRATION MOBILITYRESISTIVITY CONCENTRATION (nm/min) (—) (1/cm³) (cm²/Vs) (Ωcm) RATIO (—)WE5 25.7 0.50 2.5E+19 1,090 2.3E−04 — WE6 24.8 0.54 2.7E+19 1,0502.2E−04 — WE7 25.3 0.57 3.0E+19 1,030 2.1E−04 — WE8 24.8 0.68 3.8E+191,000 1.6E−04 0.04

FIG. 3 shows how the electron concentration changes as the IV/III ratiochanges, and FIG. 4 shows how the mobility changes as the IV/III ratiochanges. FIG. 5 shows the relation between the electron concentrationand the mobility for various IV/III ratio values. FIG. 6 shows how theelectron concentration changes as the In ratio changes, FIG. 7 shows howthe mobility changes as the In ratio changes and FIG. 8 shows how theresistivity changes as the In ratio changes. In FIGS. 3 to 5, thetriangles represent the data obtained for the first to third comparativeexamples.

Tables 1 and 2 reveal the following results. While the growth rate is15.8 nm/min to 19.0 nm/min for the first to third comparative examples,a high growth rate of 24.8 nm/min or higher is achieved for the first toeighth working examples. While the C/Si ratio in concentration for thesecond comparative example is 0.18, a low C/Si ratio in concentration isobserved for the second and eighth working examples, specificallyspeaking, 0.05 and 0.04 respectively. These results indicate that theincreased growth rate can reduce the amount of carbon atoms. The growthrate can be increased by controlling the growth conditions for the MOCVDprocess. For example, when the crystal layer growth rate is limited bythe surface reaction rate, the wafer temperature is raised to improvethe surface reaction rate of the source gas, thereby increasing thegrowth rate. Alternatively, when the crystal layer growth rate islimited by the feed rate of the Group-III source material, the flow rateof the Group III source gas is raised to increase the feed rate of theGroup III source material, thereby increasing the growth rate.

By reducing the amount of the carbon atoms, a sufficiently high electronconcentration can be obtained even with the IV/III ratio set to 0.5 orlower as shown in FIG. 3. As long as FIG. 3 is concerned, thecomparative examples (the triangles) can also achieve high electronconcentration. However, the first to third comparative examples exhibitlow mobility as seen from FIG. 4. As is apparent from the above, thefirst to fourth working examples achieve electron concentration that isnot very different from the electron concentration achieved by the firstto third comparative examples but accomplish considerably highermobility. This is probably because the first to fourth working examplesprevent the Si atoms from being implanted excessively and thus obtain ahighly pure n-type InGaAs layer. FIG. 5 shows that the first to fourthworking examples can achieve an electron concentration of 1×10¹⁹ [cm⁻³]or higher and a mobility of 1000 [cm²/Vs] or higher but the first tothird comparative examples cannot achieve a mobility of 1000 [cm²/Vs] orhigher.

FIGS. 6 to 8 show that an electron concentration of 2.5×10¹⁹ [cm⁻³] orhigher a mobility of 1000 [cm²/Vs] or higher, and a resistivity of2.3×10⁻⁴ [Ωcm] or lower are achieved even if the In ratio is relativelyhigh or 0.5 to 0.68.

DESCRIPTION OF REFERENCE NUMERALS

100 . . . semiconductor wafer, 102 . . . support wafer, 104 . . . stackstructure, 106 . . . first connection layer, 108 . . . firstsemiconductor crystal layer, 110 . . . second semiconductor crystallayer, 112 . . . third semiconductor crystal layer, 114 . . . secondconnection layer, 116 . . . fourth semiconductor crystal layer, 200 . .. heterojunction bipolar transistor (HBT), 202 . . . collectorelectrode, 204 . . . base electrode, 206 . . . emitter electrode, x . .. In ratio

What is claimed is:
 1. A semiconductor wafer comprising: a firstsemiconductor crystal layer exhibiting a first conductivity type that isone of a p-type and an n-type; a second semiconductor crystal layerexhibiting a second conductivity type that is different from the firstconductivity type; a third semiconductor crystal layer exhibiting thefirst conductivity type and having a larger band gap than the secondsemiconductor crystal layer; and a fourth semiconductor crystal layerexhibiting the first conductivity type and having a smaller band gapthan the third semiconductor crystal layer, wherein the firstsemiconductor crystal layer, the second semiconductor crystal layer, thethird semiconductor crystal layer and the fourth semiconductor crystallayer are arranged in an order of the first semiconductor crystal layer,the second semiconductor crystal layer, the third semiconductor crystallayer and the fourth semiconductor crystal layer, the fourthsemiconductor crystal layer contains a first element that generates afirst carrier corresponding to the first conductivity type and a secondelement that generates a second carrier corresponding to the secondconductivity type, the fourth semiconductor crystal layer has a carrierconcentration of 1×10¹⁹ [cm⁻³] or higher and a mobility of 1000 [cm²/Vs]or higher according to a Hall effect measurement, the fourthsemiconductor crystal layer is an In_(x)Ga_(1-x)As layer (0.4<x<0.8)exhibiting n-type conductivity, the first element is silicon, the secondelement is carbon, and the ratio in concentration of carbon to siliconin the InGaAs layer is 0.15 or lower.
 2. The semiconductor waferaccording to claim 1, wherein the fourth semiconductor crystal layer hasa carrier concentration of 2×10¹⁹ [cm⁻³] or higher and a mobility of1000 [cm²/Vs] or higher according to a Hall effect measurement.
 3. Aheterojunction bipolar transistor comprising the semiconductor waferaccording to claim 1; wherein the first semiconductor crystal layer isused as a collector layer, the second semiconductor crystal layer isused as a base layer, the third semiconductor crystal layer is used asan emitter layer, and the fourth semiconductor crystal layer is used asan emitter contact layer.
 4. A method of producing a semiconductorwafer, comprising sequentially epitaxially growing, on a wafer, a firstsemiconductor crystal layer exhibiting a first conductivity type that isone of a p-type and an n-type, a second semiconductor crystal layerexhibiting a second conductivity type that is different from the firstconductivity type, a third semiconductor crystal layer exhibiting thefirst conductivity type and having a larger band gap than the secondsemiconductor crystal layer, and a fourth semiconductor crystal layerexhibiting the first conductivity type and having a smaller band gapthan the third semiconductor crystal layer; wherein the fourthsemiconductor crystal layer is formed by means of MOCVD using a firstsource gas containing a Group-III element and a second element, a secondsource gas containing a Group-V element and a third source gascontaining a first element, the first element generates a first carriercorresponding to the first conductivity type and the second elementgenerates a second carrier corresponding to the second conductivitytype, and the fourth semiconductor crystal layer is formed with a feedrate ratio of the third source gas to the first source gas set to 0.6 orlower.
 5. The method of producing a semiconductor wafer according toclaim 4, wherein the fourth semiconductor crystal layer is formed with agrowth temperature set to 550° C. or lower.
 6. The method of producing asemiconductor wafer according to claim 4, wherein the first source gascontains an In source gas containing In and a Ga source gas containingGa, during the formation of the fourth semiconductor crystal layer, thefeed rate ratio of the In source gas to the Ga source gas is controlledso that the ratio x of In to Ga in the fourth semiconductor crystallayer is 0.4<x<0.8.